1. Field of the Invention
The invention relates to circuitry buffering the transfer of computer program instructions from a memory to an instruction processor and, in particular, to circuitry which decouples the memory controller bus width from the instruction processor bus width.
2. Description of the Prior Art
The semiconductor industry has enjoyed enormous technological advances recently. One of the most spectacular developments in the semiconductor industry has been the mass production of highly sophisticated microprocessor devices. These microprocessors perform substantially all functions which are performed by central processing units of much larger computers. A microprocessor may be combined with a few other integrated circuit devices to form a powerful yet inexpensive microcomputer system rivalling in capability large and expensive computer systems manufactured only a few years ago.
Early microprocessors were limited in the amount of information which could be simultaneously transferred in parallel to or from them. For instance, the address and data bus widths were usually limited to allow only 8 bits (i.e. 1 byte) to be transferred simultaneously between the microprocessor and other elements of the microcomputer system. This bus width restriction was a major limitation on the capabilities of the microprocessors. At the time the first microprocessors were put on the market a typical large computer system would have a central processing unit with bus widths typically in the range two to eight bytes.
In order to supply a powerful and sophisticated instruction set, the microprocessor designers developed instruction sets which included instruction of several lengths, i.e., one to three bytes. Multibyte instructions require the appropriate number of bytes to be fetched in sequence from the program memory. Substantial time is consumed in sequentially fetching the bytes forming a single instruction, limiting instruction execution rate. Single byte instruction, requiring only a single fetch from the program memory, could be executed in a much shorter period of time. In order to speed the execution of instructions, a microprocessor's instruction set would be designed to assure that the one byte instructions performed as many as possible of the most frequently desired processing functions. Less frequently used processing functions would then be allocated to the longer length instructions.
Such instruction set designs optimized the microprocessor system architecture, and compensated for the limited bus widths of the devices. As a result, the processing capability of microcomputer systems began to approach those of larger computer systems having substantially larger bus widths.
Due to the popularity of microprocessors, a vast amount of software has been written for them. A substantial investment of time and money has been made by numerous companies in software for particular microprocessors. Users of one byte bus width microprocessors wish to maintain software compatibility between these early generations of microprocessors and later generations. Due to advances in semiconductor technology, there are commercially available microprocessors having bus widths of two bytes. It is expected that in the near future there will be microprocessors having bus widths of four bytes in length. Nevertheless, these improved microprocessors will meet resistance in the marketplace unless they can execute software orginally designed to run on the one byte bus width microprocessors.
For example, the Pascal computer language was developed in the 1970's for use primarily with microprocessors. Pascal is a high-level language, which is typically compiled into "P-Code". The definition of Pascal and its P-Code has been more or less standardized. This allows a Pascal program to be executed on any computer which can execute P-Code or has a program to interpret it. P-Code contains instructions of one to four bytes in length. When a computer processor is executing P-Code, whether interpretively or directly, it must process it a byte at a time. If the computer system has a bus width allowing more than one byte at a time to be transferred between the program memory and processor, there is a difficulty in "parsing" the multiple bytes transferred simultaneously into the byte units which form P-Code instructions.
It is not desirable to transfer several bytes in parallel to the processor and have it discard all but the single byte of P-Code it desires. If this were done, the advantage of a wider bus width, namely that fewer time consuming memory accesses are required, would be nullified.
Accordingly, it is an object of the invention to provide digital logic which interfaces between a processor having an instruction set with instructions of multiples of a first size and a computer system having a system bus permitting program instruction transfers of a second size. It is another object of the invention to provide instruction fetch logic which buffers instructions fetched from program memory, providing them as requested by the processor. Yet another object of the invention is to provide a computer system in which the possible instruction lengths are independent of the bus width between the processor and remaining parts of the computer system.